Gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices by suitable HfAlO/HfON thickness and sintering temperature

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfON/HfAlO stacks and sintering temperatures were investigated in this work. Both the reduced gate leakage current and reliability improvement can be achieved by either a suitable gate dielectric stack or sintering temperature. As a whole, a 0.5 nm thick HfAlO in gate dielectric stack and a sintering temperature at 350 C are the suitable conditions for ultra-low EOT Ge MOS devices. Introduction: Since high-k gate dielectric has been implemented in metal-oxide-semiconductor field effect transistors (MOSFETs) and it generally results in mobility degradation, devices with higher carrier mobility are desirable to improve the performance of CMOS circuits. Ge has been regarded as the most promising material for improving the CMOS performance [1]. The quality of the interfacial layer (IL) between the gate dielectric and Ge substrate is very important for Ge devices [2]. Besides, the increase of the gate leakage current and the reliability degradation are the two key issues while device scaling down [2]. In this work, Ge MOS devices with different HfON/HfAlO gate stacks and sintering temperatures are studied. Experiment: The fabrication processes of Ge MOS devices were started on an n-type Ge substrate (~5 ohm-cm). After HF clean, GeO2 interfacial layer (IL) was grown by using H2O plasma process within an atomic layer deposition system (ALD). Then, various thickness stacks of HfON/HfAlO gate dielectrics were in-situ deposited by the ALD, and followed by the deposition of 30 nm TaN with a sputtering. After metallization, lithography and gate etching processes, sintering process was performed on devices at different temperatures. The detailed split conditions are shown in Table. 1. Fig. 1 shows the process flow and the schematic cross-section of the Ge MOS devices in this work. All the stress conditions for reliability tests were performed at 3.3 MV/cm. Results and Discussion: Fig. 2 and 3 show the CV curves and leakage current densities, respectively, of Ge MOS devices with different HfON/HfAlO stacks. The results indicate that both the capacitance and leakage current density decrease with increasing the thickness of HfAlO layer in HfON/HfAlO stacks. The cumulative probabilities of leakage current density for devices with different gate stacks are shown in Fig. 4, indicating that the uniformity is improved for samples with HfAlO layer. Fig. 5 shows the gate leakage currents at Vg = VFB +1 V vs EOT of Ge MOS devices with some benchmarks for comparison. Fig. 6 and 7 show the stress-induced VFB shifts and gate leakage currents, respectively, of devices with different HfON/HfAlO stacks. It is found that sample with a 0.5 nm thick HfAlO in gate dielectric stack shows the best reliability characteristics. Fig. 8 and 9 show the CV curves and leakage current densities, respectively, of the HfON gated Ge MOS devices with different sintering temperatures. The results indicate that both the capacitance and leakage current decrease with lowering the sintering temperature. Fig. 10 shows the gate leakage currents at Vg = VFB +1 V vs EOT of HfON gated Ge MOS devices with different sintering temperatures. It is seen that sample with a sintering temperature at 350 C is below the general trend line. Fig. 11 and 12 show the stress-induced VFB shifts and gate leakage currents, respectively, of HfON gated Ge MOS devices with different sintering temperatures. Thus, the reliability characteristics of high-k gate dielectric can be improved by a lower sintering temperature. Conclusions: The gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices can be achieved by a suitable HfON/HfAlO dielectric stack or sintering temperature. The optimal conditions in this work are a 0.5 nm thick HfAlO in gate dielectric stack and a sintering temperature at 350 C. References [1] P. Zimmerman et al., “High performance Ge pMOS devices using a Si-compatible process flow” IEDM, p.1-4, 2006. [2] R. Zhang et al., ” High Mobility Ge pMOSFETs with 0.7 nm Ultrathin EOT using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Post Oxidation” in VLSI Symp. Tech. Dig., p.161, 2012. ISDRS 2013, December 11-13. 2013 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 Different HfON/HfAlO2 stacks